View W19B320BB_1112158.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

w19b320bt/b datasheet publication release date: dec. 25, 2007 - 1 - revision a3 table of contents- 1. general des cription ............................................................................................................ .. 4 2. features ....................................................................................................................... ............... 5 3. pin config uration s............................................................................................................. ..... 7 4. block di agram .................................................................................................................. ......... 8 5. pin descri ption................................................................................................................ .......... 8 6. functional d escription ........................................................................................................ 9 6.1 device bus operat ion ........................................................................................................... .. 9 6.1.1 word/byte conf igurat ion ........................................................................................................ .. 9 6.1.2 reading arra y data ............................................................................................................. ..... 9 6.1.3 writing commands/c ommand s equences ............................................................................... 9 6.1.4 standby mode ................................................................................................................... ..... 10 6.1.5 automatic sleep m ode ........................................................................................................... 10 6.1.6 #reset: hardware reset pin................................................................................................ 10 6.1.7 output dis able m ode............................................................................................................ .. 11 6.1.8 autoselec t mode ................................................................................................................ ..... 11 6.1.9 sector/sector block prot ection and unpr otecti on................................................................... 11 6.1.10 write protec t (#wp)............................................................................................................ .... 11 6.1.11 temporary sector unprot ect .................................................................................................. 12 6.1.12 security sector fl ash memory regi on ................................................................................... 12 6.1.13 hardware data protec tion ...................................................................................................... 13 6.2 command defi nitions............................................................................................................ 13 6.2.1 reading arra y data ............................................................................................................. ... 13 6.2.2 reset co mmand.................................................................................................................. ... 14 6.2.3 autoselect co mmand s equence ..................................................................................... 14 6.2.4 byte/word program command sequenc e.............................................................................. 15 6.2.5 unlock bypass co mmand s equence ..................................................................................... 15 6.2.6 chip erase co mmand s equence ........................................................................................... 16 6.2.7 sector erase command s equence ........................................................................................ 16 6.2.8 erase suspend/erase resume comm ands ........................................................................... 17 6.3 write operat ion st atus......................................................................................................... . 17 6.3.1 dq7: #dat a pollin g............................................................................................................. .... 17 6.3.2 ry/#by: r eady/#bu sy ........................................................................................................... 18 6.3.3 dq6: toggl e bit i .............................................................................................................. ...... 18 6.3.4 dq2: toggl e bit ii ............................................................................................................. ...... 19 6.3.5 reading toggle bi ts dq6/dq2............................................................................................... 19 6.3.6 dq5: exceeded ti ming li mits ................................................................................................ 19
w19b320bt/b datasheet publication release date:dec.25, 2007 - 2 - revisionv a3 6.3.7 dq3: sector erase ti mer ....................................................................................................... 20 7. table of oper ation modes ................................................................................................. 21 7.1 device bus operat ions ......................................................................................................... 21 7.2 autoselect codes (h igh voltage method) ..................................................................... 22 7.3 sector address tabl e (top boot block) ............................................................................... 23 7.4 sector address table (bottom boot block) .......................................................................... 25 7.5 top boot sector/sector block addr ess for protecti on/unprot ection) ................................... 27 7.6 cfi query identif ication string.............................................................................................. 29 7.6.1 system interf ace st ring ........................................................................................................ .. 29 7.6.2 device geometry defini tion .................................................................................................... 30 7.6.3 primary vendor-specif ic extended query .............................................................................. 31 7.6.4 command defi niti ons ............................................................................................................ . 32 7.6.5 write operat ion st atus ......................................................................................................... .. 33 7.7 temporary sector u nprotect al gorithm ................................................................................ 33 7.8 in-system sector protec t/unprotect al gorithms ................................................................... 35 7.9 security sector protect verify ............................................................................................... 36 7.10 program al gorit hm .............................................................................................................. .. 36 7.11 erase al gorit hm................................................................................................................ ..... 37 7.12 data polling algorit hm......................................................................................................... .. 37 7.13 toggle bit algorit hm........................................................................................................... ... 38 8. electrical cha racteris tics.............................................................................................. 39 8.1 absolute maxi mum ratings .................................................................................................. 39 8.2 operati ng r anges ............................................................................................................... .. 39 8.3 dc characte ristics ............................................................................................................. ... 40 8.4 cmos com patible ................................................................................................................ 40 8.5 ac characte ristics ............................................................................................................. ... 41 8.6 test c onditi on ................................................................................................................. ...... 41 8.6.1 ac test load and wave forms ............................................................................................... 41 8.7 read-only o perati ons .......................................................................................................... 42 8.8 hardware rese t (#reset)................................................................................................... 42 8.9 word/byte confi guration (#byte) ........................................................................................ 42 8.10 erase and program operation .............................................................................................. 43 8.11 temporary sector unprotect................................................................................................. 43 8.12 alternate #ce controlled er ase and program operat ions ................................................... 44 9. timing w aveforms ............................................................................................................... ... 45 9.1 ac read wa veform .............................................................................................................. 45
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 3 - revisionv a3 9.2 reset wa veform ................................................................................................................. .. 45 9.3 #byte waveform fo r read oper ation.................................................................................. 46 9.4 #byte waveform for write oper ation.................................................................................. 46 9.5 programming wavefo rm ....................................................................................................... 47 9.6 accelerated progr amming wa veform ................................................................................... 47 9.7 chip/sector er ase wave form ............................................................................................... 48 9.8 back-to back read/write cycle wa veform........................................................................... 48 9.9 #data polling waveform (d uring embedded al gorithm s) .................................................... 49 9.10 toggle bit waveform (d uring embedded al gorithm s).......................................................... 49 9.11 dq 2 vs. dq 6 wave form ...................................................................................................... 50 9.12 temporary sector unpr otect timi ng diagr am ...................................................................... 50 9.13 sector/sector block protect and unprotect ti ming di agram................................................ 50 9.14 alternate #ce controlled write (e rase/program) o peration timing .................................... 51 10. latchup chara cteristics ................................................................................................... 52 11. capacit ance.................................................................................................................... .......... 52 12. ordering in format ion.......................................................................................................... 53 13. package dime nsio ns ............................................................................................................. . 54 13.1 tfbga48ball (6x8 mm^ 2, ?=0. 40mm) ................................................................................ 54 13.2 48-pin standard thin sm all outli ne pack age ...................................................................... 55 14. version hi story ................................................................................................................ ...... 56
w19b320bt/b datasheet publication release date:dec.25, 2007 - 4 - revisionv a3 1. general description the w19b320bt/b is a 32mbit, 2.7~3.6-volt single bank cmos flash memory organized as 4m x 8 or 2m 16 bits. the word-wide ( 16) data appears on dq15-dq0, and byte-wide (x 8) data appears on dq7-dq0. the device can be programmed and eras ed in-system with a standard 3.0-volt power supply. a 12-volt v pp is not required. the unique cell architectu re of the w19b320bt/b results in fast program/erase operations with extremely low curr ent consumption (compared to other comparable 3- volt flash memory products). the device can also be programmed and erased by using standard eprom programmers.
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 5 - revisionv a3 2. features performance ? 2.7~3.6-volt write (progr am and erase) operations ? fast write operation ? sector erases time: 0.4 sec (typical) ? chip erases time: 30sec (typical) ? byte/word programming time: 7/9 s (typical) ? read access time: 70 ns ? typical program/erase cycles: 100k ? twenty-year data retention ? ultra low power consumption ? active current (read): 10 ma (typical) ? active current (read while erase): 21 ma (typical) ? standby current: 0.2 a (typical) architecture ? sector erase architecture ? eight 8kb, and sixty-three 64kb sectors ? top or bottom boot block configurations available ? supports full chip erase ? security sector size: 256 bytes ? the security sector is an otp; once the se ctor is programmed, it cannot be erased ? jedec standard byte-wi de and word-wide pinouts ? manufactured on winstack 0.13 m process technology ? available packages: 48-pin tsop and 48-ball tfbga (6x8mm) software features ? compatible with common flash memo ry interface (cfi) specification ? flash device parameters st ored directly on the device ? allows software driver to identify and use a vari ety of different current and future flash products ? erase suspend/erase resume ? suspends erase operations to allow programming in same bank ? end of program detection ? software method: toggle bit/data polling ? unlock bypass program command ? reduces overall programming time when i ssuing multiple program command sequences
w19b320bt/b datasheet publication release date:dec.25, 2007 - 6 - revisionv a3 hardware features ? ready/#busy output (ry/#by) ? detect program or erase cycle completion ? hardware reset pin (#reset) ? reset the internal state machine to the read mode ? #wp/acc input pin ? write protect (#wp) function allows protection of two outermost boot sectors, regardless of sector protection status temperature range ? extended temperature range (-20 to 85 ) ? industrial devices ambient temperature(-40 to +85 )
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 7 - revisionv a3 3. pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 dq15/a-1 a9 a10 a11 a12 a13 a14 a15 #oe 48-pin tsop 24 23 a17 a16 #we #ce a7 a6 a5 a4 a3 a2 a1 a0 21 22 48 47 46 45 44 43 42 41 #wp/acc nc a18 ry/#by #reset a20 a19 dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 v dd dq7 dq14 dq6 dq13 dq5 dq12 dq4 #byte vss vss a8 48-ball tfbga (top view, balls face down) a6 a5 a4 a3 a2 a1 #ce a3 b6 b5 b4 b3 b2 b1 c6 c5 c4 c3 c2 c1 d6 d5 d4 d3 d2 d1 e6 e5 e4 e3 e2 e1 f6 f5 f4 f3 f2 f1 g6 g5 g4 g3 g2 g1 h6 h5 h4 h3 h2 h1 a4 a2 a1 a0 #oe a7 a17 a6 a5 dq0 dq8 dq9 dq1 ry/#by a18 a20 dq2 dq10 dq11 dq3 #wp/acc #we #reset nc a19 dq5 dq12 v dd dq4 a9 a8 a10 a11 dq7 dq14 dq13 dq6 a13 a12 a14 a15 a16 #byte dq15/a-1 vss vss
w19b320bt/b datasheet publication release date:dec.25, 2007 - 8 - revisionv a3 4. block diagram decoder control output buffer #ce #oe #we a0 a20 . . . dq0 dq15/a-1 . . v v dd ss bank dq15/a-1 #wp/acc #byte #reset 5. pin description symbol pin name a0 ? a20 address inputs dq0 ? dq14 data inputs/outputs word mode dq15 is data inputs/outputs dq15/a-1 byte mode a-1 is address input #ce chip enable #oe output enable #we write enable #wp/acc hardware write protect/ acceleration pin #byte byte enable input #reset hardware reset ry/#by ready/busy status v dd power supply v ss ground nc no connection
w19b320bt/b datasheet publication release date: dec. 25, 2007 - 9 - revision a3 6. functional description 6.1 device bus operation 6.1.1 word/byte configuration the #byte pin controls the device data i/o pins operat e whether in the byte or word configuration. when the #byte pin is ?1?, the device is in word configuration; dq0 -dq15 are active and controlled by #ce and #oe. when the #byte pin is ?0?, the device is in byte configuration, and only data i/o pins dq0-dq7 are active and controlled by #ce and #oe. the data i/o pins dq8-dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. 6.1.2 reading array data to read array data from the outputs, the #ce and #oe pins must be set to v il . #ce is the power control and used to select the device. #oe is the output control and gates array data to the output pins. #we should stay at v ih . the #byte pin determines the device out puts array data whether in words or bytes. the internal state machine is set for reading a rray data when device power-up, or after hardware reset. this ensures that no excess modification of the memory content occurs during the power transition. in this mode there is no command nece ssary to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. each bank remains enabled for read access until the command register contents are changed. 6.1.3 writing commands/command sequences in writhing a command or command sequence (which includes programming data to the device and erasing sectors of memory), t he system must drive #we and #ce to v il , and #oe to v ih . for program operations, the #byte pin determines the device accepts program data whether in bytes or in words. refer to ?word/byte conf iguration? for more information. the unlock bypass mode of device is to facilitat e a faster programming. when a bank enters the unlock bypass mode, only two write cycles are requir ed to program a word or byte. please refer to "word/byte configuration? section for details on programming data to the device using both standard and unlock bypass command sequences. the erase operation can erase a sector, multiple se ctors, even the entire devic e. the ?sector address? is the address bits required to solely select a sector. accelerated program operation the device provides accelerated program operations through the acc function. this is one of two functions provided by the #wp/a cc pin. this function is primarily intended to allow a faster manufacturing throughput in the factory. if #wp/acc pin is set at v hh , the device automatically enters in to the unlock bypass mode. then the device will temporarily unprotect any protected sect ors, and uses the higher voltage on this pin to reduce the time required for program operations . the system would use a two-cycle program command sequence required by the unlock bypass mode. when v hh is removed from the #wp/acc pin, the device is back to a normal operation.
w19b320bt/b datasheet publication release date:dec.25, 2007 - 10 - revisionv a3 please note that the #wp/ acc pin can not be at v hh for operations except accelerated programming; otherwise, the device will be damaged. in addition, the #wp/acc pin can not be left floating; otherwise, an unconnected inconsistent behavior will occur. autoselect functions when the system writes the autoselec t command sequence, the device enters the autoselect mode. the system can then read auto select codes from the internal register (which is separate from the memory array) on dq0 ?dq7. the standard read cycle timings are applied in this mode. please refer to the autoselect mode and autoselect command sequence sections for more information. 6.1.4 standby mode when the system is not reading or writing to the device, the device will be in a standby mode. in this mode, current consumption is greatly reduced, and the outputs are in the high impedance state, independent from the #oe input. when the #ce and #reset pins are both held at v dd 0.3v, the device enters into the cmos standby mode (note that this is a more restricted voltage range than v ih .) when #ce and #reset are held at v ih , but not within v dd 0.3v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. when the device is deselected during erasing or progr amming, the device initiates active current until the operation is completed. 6.1.5 automatic sleep mode the automatic sleep mode minimizes device's energy consumption. when addresses remain stable for t acc + 30ns, the device will enable this mode aut omatically. the automatic sleep mode is independent from the #ce , #we , and #oe control signals. standard addre ss access timings provide new data when addresses are changed. in sleep mode, output data is latched and always available to the system. 6.1.6 #reset: hardware reset pin the #reset pin provides a hardware method to re set the device to reading array data. when the #reset pin is set to low for at least a period of t rp , the device will immediately terminate every operation in progress, tri-states all output pins, and ignores all read/write commands for the duration of the #reset pulse. the device also resets the internal state machine to reading array data mode. to ensure data integrity, the interrupted operation needs to be reinitiated when the device is ready to accept another command sequence. current is reduced for the duration of t he #reset pulse. when #reset is held at v ss 0.3v, the device initiates the cm os standby current (i cc4 ). if #reset is held at v il but not within v ss 0.3v, the standby current will be greater. the #reset pin may be tied to the system-reset circuitry. thus the system reset would also reset the device, enabling the system to read t he boot-up firmware from the device. if #reset is asserted during the progr am or erase operation, the ry/#by pin will be at ?0? (busy) until the internal reset operation is complete. if #reset is asserted when a program or erase operation is not processing (ry/#by pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms). after the #reset pin returns to v ih , the system can read data t rh.
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 11 - revisionv a3 6.1.7 output disable mode when the #oe input is at v ih , output from the device is disabled. the output pins are set in the high impedance state. 6.1.8 autoselect mode the autoselect mode offers manufacturer and device identification, as well as sector protection verification, through identifier codes output on dq0-dq7. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (8.5v to 11.5v) on address pins a9. address pins a6, a1, and a0 must be as shown in table. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. when all necessary bits have been set as requir ed, the programming equipment may then read the corresponding identifier code on dq0-dq7. 6.1.9 sector/sector block protection and unprotection the hardware sector protection feature disables bot h program and erasure operations in any sectors. the hardware sector unprotection feature re- enables both program and erasure operations in previously protected sectors. sector protection/unprotecti on can be implemented through two methods. the primary method requires v id on the #reset pin, and can be implemented either in-system or through programming equipment. this method uses standard microprocessor bus cycle timing. the alternate method intended only for programming equipment requires v id on address pin a9 and #oe. it is possible to determine whether a sector is protected or unprotected. see the application note for detail information. 6.1.10 write protect (#wp) the write protect function provides a hardware me thod to protect the cert ain boot sectors without using v id . this function is one of two featur es provided by the #wp/acc pin. when the #wp/acc pin is set at v il , the device disables program and erase functions in the two outermost 8 kbytes boot sector s independently of whether those sectors were protected or unprotected using the method described in ?sector/ sector block protection and unprotection.? the two outermost 8 kbytes boot sectors are the two se ctors containing either t he lowest addresses in a bottom-boot-configured device or the highest addresses in a top-boot-configured device. when the #wp/acc pin is set at v ih , the device reverts to the two outermost 8 kbytes boot sectors were last set either to be protect ed or unprotected. that is, sector protection or unprotection for these two sectors depends on whether they were last pr otected or unprotected us ing the method described in ?sector/sector block protection and unprotection?. please note that the #wp/acc pin must not be left floating or unconnected; otherwise, the inconsistent behavior of the device may occur.
w19b320bt/b datasheet publication release date:dec.25, 2007 - 12 - revisionv a3 6.1.11 temporary sector unprotect this feature allows temporary u nprotection of previously protect ed sectors to change data in-system. when the #reset pin is set to v id , the sector unprotect mode is activated. during this mode, formerly protected sectors can be programmed or er ased by selecting the sect or addresses. what if v id is removed from the #reset pin, all the prev iously protected sector s are protected again. 6.1.12 security sector flash memory region the security sector feature provides an ot p memory region that enables permanent device identification through an electronic serial number (esn ). the security sector uses a security sector indicator bit (dq7) to indicate whether the securi ty sector is locked or not when shipped from the factory. the dq7 is permanently set when it is in the factory and cannot be changed, which prevents copying of a factory locked part. this ensures the security of the esn when the product is shipped to the field. this issue should be considered during system design. winbond offe rs the device with the security sector either factory locked or customer lockable. the factory-locked version is always protected when shipped from the factory, and has the security sector indicator bit permanently set to ?1? the customer-lockable version is shipped with the security sector unprotected, which allowing customers to utilize the sector in any ways they choose. the customer-lockable version has the security sector indicator bit permanently set to ?0.? thus, the security sector indicator bit prevents customer-lockable devices from being used to replace devices that are factory locked. the system accesses the security sector through a command sequence (see ?enter security sector/exit security sector command sequence?). a fter the system has written the enter security sector command sequence, it may read the securi ty sector by using the addresses normally occupied by the boot sectors. th is mode of operation continues unt il the system issues the exit security sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. factory locked: security sector programmed and protected at the factory the device security sector is protected when it is shipped from the factory, and it cannot be modified in any way. the device is available to be preprogrammed by one of the following: ? a random, secure esn only ? customer code through the supplier's service ? both a random, secure esn and customer code through supplier's service. in devices with an esn, the bottom boot device will be with the 16-byte esn in the lowest addressable memory area at addresses 000000h?000007h in word mode (or 000000h?00000fh in byte mode). in the top boot devic e the starting address of the esn w ill be at the bottom of the highest 8 kbytes boot sector at addresses 1ff 000h?1ff007h in word mode (or addresses 3fe000h? 3fe00fh in byte mode). customers may choos e have their code programmed by winbond. winbond can program the customer?s code, with or without the random esn. the devices are then shipped with the security sector permanently locked. customer lockable: security sector not programmed or protected at the factory if the security feature is not nec essary, the security sector can be seen as an additional otp memory space. when in system design, this issue should be considered. the security sector can be read, programmed; but cannot be erased. please note t hat when programming the security sector, the accelerated programming (acc) and unlock bypass functi ons are not available. the security sector area can be protected using one of the following procedures:
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 13 - revisionv a3 ? write the three-cycle enter security sect or region command sequence, and then follow the in-system sector protect algorithm, except that #reset may be at either v ih or v id . this allows in-system protection of the security se ctor without raising any device pin to a high voltage. please note that this method is only suitable for the security sector. ? to verify the protect/unprotect status of the security sector; follow the algorithm show in security sector protect verify. the security sector protection must be used with caution, since there is no procedure available for unprotect the security sector area and none of the bits in the security sector memory space can be modified in any ways. 6.1.13 hardware data protection the command sequence requirements of unlock cycles for programming or erasing provides data protection against negligent writes. in addition, the following hardware data protection measures prevent inadvertent erasure or pr ogramming, which might be caused by spurious system level signals during v dd power-up and power-down transiti ons, or from system noise. write pulse ?glitch? protection noise pulses, which is less than 5 ns (typical) on #o e, #ce or #we, do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of #oe = v il , #ce = v ih or #we = v ih . #ce and #we must be a logical zero while #oe is a logical one to initiate a write cycle. power-up write inhibit during power up, if #we = #ce = v il and #oe = v ih , the device does not accept commands on the rising edge of #we. the internal state machine is automatically reset to the read mode on power-up. 6.2 command definitions the device operation can be initiated by writi ng specific address and data commands or sequences into the command register. the device will be rese t to reading array data when writing incorrect address and data values or writing them in the improper sequence. the addresses will be latched on the falling edge of #we or #ce, whichever happens later; while the data will be latched on the rising edge of #we or #ce, whichever happens first. please refer to timing waveforms. 6.2.1 reading array data after device power-up, it is automatically set to reading array data. there is no commands are required to retrieve data. after completi ng an embedded program or embedded erase algorithm, each bank is ready to read array data. after the device accepts an erase suspend co mmand, the corresponding bank enters the erase- suspend-read mode. after it the system can read data from any non-erase-suspended sector within the same bank. and then, after completing a progr amming operation in the erase suspend mode, the system may once again read array data with t he same exception. please refer to erase suspend/erase resume commands section for detail information.
w19b320bt/b datasheet publication release date:dec.25, 2007 - 14 - revisionv a3 the system must initiate the reset command to re turn a bank to read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or the bank is in the autoselect mode. see reset command section and requirements for reading array data in the device bus operations section for more information. 6.2.2 reset command the banks will be to the read or erase-suspend-read mode when writing the reset command. for this command, the address bits are don?t care. the reset command may be written between the sequential cycles in an erase command sequence before erasing begins. this resets the bank to whic h the system was writing to the read mode. once erasure begins, however, the device ignores re set commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the bank, to which the system was wr iting to the read mode. if the program command sequence is written to a bank , in the erase suspend mode, writing the reset command returns that bank to the erase-sus pend-read mode. when programming begins, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. when in the autoselect mode, the reset command must be written to return to the read mode. if a bank entered into the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend). 6.2.3 autoselect command sequence the autoselect command sequence provides the host system to access the manufacturer and device codes, and determine whether a sector is protec ted or not. this is an alternative method, which is intended for prom programmers and requires v id on address pin a9. the autoselect command sequence may be written to an address within a bank that is either in the read or erase- suspend-read mode. when the device is actively programming or erasing in the other bank, the autoselect command may not be written. the first writing two unlock cycles initiate t he autoselect command sequence. this is followed by a third write cycle that contains the bank address and the autoselect command. the bank then enters into the autoselect mode. the system may read at any address within the same bank without initiating another autoselect command sequence: ? a read cycle at address (ba) xx00h (where ba is the bank address) returns the manufacturer code. ? a read cycle at address (ba) xx01h in word mode (or (ba) xx02h in byte mode) returns the device code. ? a read cycle to an address containing a sector ad dress (sa) within the same bank, and the address 02h on a7-a0 in word mode (or the address 04h on a6-a-1 in byte mode) returns 01h if the sector is protected or 00h if it is unprotected. to return to read mode (or erase-suspend-read mode if the bank was previously in erase suspend), the system must write the reset command. enter security sector/exit security sector command sequence the security sector region provides a secured data area containing a random, sixteen-byte electronic serial number (esn). the system can access the se curity sector region by issuing the three-cycle
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 15 - revisionv a3 enter security sector command sequence. the device continues to access the security sector region until the system issues the four-c ycle exit security sector co mmand sequence. the exit security sector command sequence returns the device to nor mal operation. see ?security sector flash memory region? for further information. 6.2.4 byte/word program command sequence the device can be programmed either by word or byte, which depending on the state of the #byte pin. programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by t he program setup command. the program address and data are written next, which in turn initiate t he embedded program algorithm. the device automatically provides internally generated program pulses and verifies the programmed cell margin. once the embedded program algorithm is complete, the bank then returns to the read mode and addresses are no longer latched. the system can det ermine the status of t he program operation by using dq7, dq6, or ry/#by. please refer to the write operation status section for bits' information. any commands written to the device duri ng the embedded program algorithm are ignored. please note that a hardware reset will immediately stop the program operation. the program command sequence should be reinitiated when the bank has retu rned to the read mode, in order to ensure data integrity. programming is allowed in any sequence and acro ss sector boundaries. a bit cannot be programmed from ?0? back to ?1.? if trying to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate that the operation is su ccessful. however, a succeeding read will show that the data is still ?0.? only erase oper ations can change ?0? to ?1.? 6.2.5 unlock bypass command sequence the unlock bypass feature provides the system to program bytes or words to a bank which is faster than using the standard program command sequenc e. the unlock bypass command sequence is initiated by first writing two unlock cycles. a nd a third write cycle c ontaining the unlock bypass command, 20h, is followed. then, the bank enters into the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that required to program in this mode. the first cycle in this sequence contains the unlock bypass program co mmand, a0h; the second cycle contains the program address and data. in the same manner, additi onal data is programmed. this mode dispenses with the initial two unlock cycles which r equired in the standard program command sequence, resulting in faster total programming time. all through the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. the system must issue t he two-cycle unlock bypass reset command sequence to exit the unlock bypass mode. the first cycle must contain t he bank address and the data 90h. the second cycle needs to contain the data 00h. then, the bank returns to the read mode. the device offers accelerated program oper ations by the #wp/ acc pin. when the v hh is set at the #wp/acc pin, the device automatic ally enters into the unlock by pass mode. then, the two-cycle unlock bypass program command sequence may be writt en. to accelerate the operation, the device must use the higher voltage on the #wp/acc pin. pl ease note that the #wp/a cc pin must not be at v hh in any operation other than accelerated progr amming; otherwise the device may be damaged. in addition, the #wp/acc pin must not be left floating or unconnected; otherwise the device inconsistent behavior may occur.
w19b320bt/b datasheet publication release date:dec.25, 2007 - 16 - revisionv a3 6.2.6 chip erase command sequence chip erase is a six-bus cycle operation. writing tw o unlock cycles initiate the chip erase command sequence, which is followed by a set-up command. after chip erase command, two additional unlock write cycles are then followed, which in turn invokes the embedded erase algorithm. the system preprogram is not required prior to erase. befo re electrical erase, the embedded erase algorithm automatically preprograms and verifies the entire memo ry for an all zero data pattern. any controls or timings during these operations is not required in system. as the embedded erase algorithm is complete, the bank returns to the read mode and addresses are no longer latched. the system can determine the status of the eras e operation by using dq7, dq6, dq2, or ry/#by. please refer to the write operati on status section for info rmation on these status bits. any commands written during the chip erase operat ion will be ignored. however, a hardware reset shall terminate the erase operation immediately. if this happens, to ensure data integrity, the chip erase command sequence should be reinitiated when t hat bank has returned to reading array data. 6.2.7 sector erase command sequence sector erase is a six-bus cycle operation. writing tw o unlock cycles initiate the sector erase command sequence, which is followed by a set-up command. two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. the device does not require the system to preprogram before erase. before electrical erase, the embedded erase algorithm automatically programs and ve rifies the entire memory for an all zero data pattern. any controls or timings during t hese operations are not required in system. a sector erase time-out of 50 s occurs after the command sequence is written. additional sector addresses and sector erase commands may be written during the time-out period. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these addi tional cycles must be less than 50 s; otherwise, erasure may begin. any sector erase address and command follo wing the exceeded time-out may or may not be accepted. to ensure all commands are accepted, proc essor interrupts be disabled during this time is recommended. the interrupts can be re-enabled after t he last sector erase command is written. any command other than sector erase or erase suspend dur ing the time-out period resets the bank to the read mode. the system must rewrite the comm and sequence and any additional addresses and commands. the system can monitor dq3 to determine whether or not the sector erase timer has timed out (see the section on dq3: sector erase timer.). the ti me-out begins from the rising edge of the final #we pulse in the command sequence. as the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. please note that when t he embedded erase operation is in progress, the system can read data from the non-erasing bank at the same time. by reading dq7, dq6, dq2, or ry/#by in the erasing bank, the system can determine the status of the eras e operation. please refer to the write operation status section for information on these status bits. when the sector erase operation begins, only t he erase suspend command is valid. all other commands are ignored. however, a hardware reset s hall terminate the erase operation immediately. if
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 17 - revisionv a3 this occurs, to ensure data integrity, the sect or erase command sequence should be reinitiated once the bank has returned to reading array data. 6.2.8 erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. when writing this command, the bank address is required. this command is valid only during the sector erase operation, which includes the 50 s time-out period during the sector eras e command sequence. if written during the chip erase operation or embedded program algor ithm, the erase suspend command is ignored. as the erase suspend command is written during the sector erase operation, a maximum of 20 s is required to suspend the erase operation. howeve r, while the erase suspend command is written during the sector erase time-out, the device sha ll terminate the time-out period and suspends the erase operation immediately. the bank enters into an erase-suspend-read m ode after the erase operation has been suspended. the system can read data from, or program data to, any sector not selected for erasure. (in device ?erase suspends? all sectors are selected for er asure.) the ?reading at any address within erase- suspended sectors produces status? information is on dq0-dq7. the system can use dq7, or dq6 and dq2 together, to determine whether a sector is actively erasing or is erase-suspended. please refer to the write operation status section for detail information on these status bits. after an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. using the dq7 or dq6 status bits, the system can determine the status of the program operation, just as in the standard byte program operation. please refer to the write operation status section for more information. in the erase-suspend-read mode, the autoselect command sequence also can be issued. please refer to the autoselect mode and autoselect command sequence sections for details. the erase resume command must be written to resume the sector erase operation. when writing this command, the bank address of the erase-suspended bank is required. further writes of the resume command are ignored. after the chip has resumed erasing, another erase suspend command can be written. 6.3 write operation status the device provides several bits to determine the st atus of a program or er ase operation: dq2, dq3, dq5, dq6, and dq7. each of dq7 and dq6 provides a method for determining whether a program or erase operation is complete or in progress. t he device also offers a hardware-based output signal, ry/#by, to determine whether an embedded program or erase operation is in progress or has been completed. 6.3.1 dq7: #data polling the #data polling bit, dq7, indicates whether an embedded program or erase algorithm is in progress or completed, or whether or not a bank is in erase suspend. data polling is valid after the rising edge of the final #we pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 and the complement of the data programmed to dq7. this dq7 status also applie s to programming during erase suspend. once the embedded program algorithm has completed that t he device outputs the data programmed to dq7. the system must provide the progr am address to read valid status information on dq7. if a program
w19b320bt/b datasheet publication release date:dec.25, 2007 - 18 - revisionv a3 address falls within a protected sector, #data polling on dq7 is active for about 1 s, and then that bank returns to the read mode. during the embedded erase algorithm, #data po lling produces ?0? on dq7. once the embedded erase algorithm has completed, or when the bank enters the erase suspend mode, #data polling produces ?1? on dq7. an address within any of the sectors selected for erasure must be provided to read valid status information on dq7. after an erase command sequence is written, if all se ctors selected for erasi ng are protected, #data polling on dq7 is active for about 100 s, and then the bank returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if t he system reads dq7 at an address within a protected sector, the status may not be valid. just before the completion of an embedded pr ogram or erase operation, dq7 may change asynchronously with dq0-dq6 while output enable (#oe) is set to low. that is, the device may change from providing status information to va lid data on dq7. depending on when it samples the dq7 output, the system may read the status or va lid data. even if the dev ice has completed the program or erase operation and dq7 has valid data, the data outputs on dq0-dq6 may be still invalid. valid data on dq0-dq7 will appear on successive read cycles. 6.3.2 ry/#by: ready/#busy the ry/#by is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/#by status is valid after the rising edge of the final #we pulse in the command sequence. since ry/#by is an open-drain output, several ry/#by pins can be tied together in parallel with a pull-up resistor to v dd . when the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) when the output is high (ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. 6.3.3 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded progr am or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final #we pulse in the command sequence (before the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operati on, successive read cycles to any address cause dq6 to toggle. the system may use either #oe or #ce to control the read cycles. once the operation has completed, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for about 100 s, and then returns to reading array dat a. if not all selected sectors are protected, the embedded erase algorithm erases t he unprotected sectors, and ignores the selected sectors which are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. if the device is ac tively erasing (i.e., the embedded er ase algorithm is in progress), dq6 toggles. while if the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sect ors are erasing or erase-suspended. alternatively, the system can use dq7 (see dq7: #data polling).
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 19 - revisionv a3 if a program address falls within a protected sector, dq6 toggles for about 1 s after the program command sequence is written, and then returns to reading array data. dq6 also toggles during the erase-suspend-pr ogram mode, and stops toggling when the embedded program algorithm is complete. please also refer to dq2: toggle bit ii. 6.3.4 dq2: toggle bit ii when used with dq6, the ?toggle bit ii? on dq2 indicates whether a particular sector is actively erasing (i.e., the embedded erase algorithm is in progress), or t he sector is erase-suspended. toggle bit ii is valid after the rising edge of the final #we pulse in the command sequence. dq2 toggles as the system reads at addresses within those sectors that have been selected for erasure. (the system may use either #oe or #ce to control the read cycles.) but dq2 cannot distinguish that whether the sector is actively erasing or is erase-suspended. by comparison, dq6 indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. therefore, both status bits are required for sector and mode information. 6.3.5 reading toggle bits dq6/dq2 whenever the system initially starts to read toggle bit status, it must read dq0-dq7 at least twice in a row to determine whether a toggle bit is toggling or not. typically, the system would note and store the value of the toggle bit after the first read. while after the second read, the system would compare the new value of the toggle bit with the first one. if the toggle bit is not toggling, the device has completed the program or erasure operation. the system can read array data on dq0-dq7 on the following read cycle. however, if after the initial two read cycles, the system finds that the toggle bit is still toggling, the system also should note whether the value of dq5 is high or not(see the section on dq5). if dq5 is high, the system should then determine again whether the toggle bit is toggling or not, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erasure operation. if it is still toggling, the device did not complete the operation, and the system must write the reset command to return to reading array data. then the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, and determines the status as described in the previous paragraph. alternatively, the system may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm while it returns to determine the status of the operation. 6.3.6 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. dq5 produces ?1? under these conditions which indica tes that the program or erase cycle was not successfully completed. the device may output ?1? on dq5 if the system tries to program ?1? to a location that was previously programmed to ?0.? only the erase operation can change ?0? back to ?1.? under this condition, the device stops the operation, and while the timing limit has been exceeded, dq5 produces ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
w19b320bt/b datasheet publication release date:dec.25, 2007 - 20 - revisionv a3 6.3.7 dq3: sector erase timer after writing a sector erasure command sequence, the system may read dq3 to determine whether erasure has begun or not. (the sector erase timer does not apply to the chip erase command.) the entire time-out applies after each additional sector erasure command if additional sectors are selected for erasure. once the timeout period has completed, dq3 switches from ?0? to ?1.? if the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor, dq3 does not need to be monitored. please also refer to sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 ( #data polling ) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is?1,? the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. the system software should check the status of dq3 before and following each subsequent sector erase command to ensure the command has been accepted. if dq3 is high on the second status check, the last command might not have been accepted.
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 21 - revisionv a3 7. table of operation modes 7.1 device bus operations dq8-dq15 mode #ce #oe #we #reset #wp/acc addresses dq0-dq7 #byte=v ih #byte =v il read l l h h l/h a in d out d out write l h l h (note2) a in d in d in dq8-dq14 =high-z, dq15=a-1 standby v dd 0.3v x x v dd 0.3v h x high-z high-z high-z output disable l h h h l/h x high-z high-z high-z reset x x x l l/h x high-z high-z high-z sector protect l h l v id l/h sa, a6=l, a1=h, a0=l d in x x sector unprotect l h l v id (note2) sa, a6=h, a1=h, a0=l d in x x temporary sector unprotect x x x v id (note2) a in d in d in high-z legend: l = logic low = v il , h = logic high = v ih , v id = 8.5 ~ 11.5 v, v hh = 9.0 0.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out. notes: 1. addresses are a20:a0 in word mode (#byte = v ih ), a20: a-1 in byte mode (#byte = v il ). 2. if #wp/acc = v il , the two outermost boot sectors remain protected. if #wp/acc = v ih , the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in ?sector/sector block protection and unprotect ion?. if #wp/acc = v hh , all sectors will be unprotected.
w19b320bt/b datasheet publication release date:dec.25, 2007 - 22 - revisionv a3 7.2 autoselect codes (high voltage method) dq8 to dq15 description #ce #oe #we a20 to a12 a 11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 #byte = v ih #byte = v il dq7 to dq0 manufacturer id: winbond v il v il v ih xxv id x vil xv il v il x x dah device id: w19b320bt (top boot block) v il v il v ih xxv id x vil xv il v ih 22h x bah device id: W19B320BB (bottom boot block) v il v il v ih xxv id xv il xv il v ih 22h x 2ah sector protection verification v il v il v ih sa x v id x vil xv ih v il x x x x 01h (protected ) 00h (unprotected) security indicator bit (dq7) v il v il v ih xxv id x vil xv ih v ih x x 82h (factory locked) 02h (not factory locked) legend: sa= sector address, x= don't care.
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 23 - revisionv a3 7.3 sector address table (top boot block) sector sector address a20-a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 000000xxx 64/32 000000h-00ffffh 000000h-07fffh sa1 000001xxx 64/32 010000h-01ffffh 008000h-0ffffh sa2 000010xxx 64/32 020000h-02ffffh 010000h-17fffh sa3 000011xxx 64/32 030000h-03ffffh 018000h-01ffffh sa4 000100xxx 64/32 040000h-04ffffh 020000h-027fffh sa5 000101xxx 64/32 050000h-05ffffh 028000h-02ffffh sa6 000110xxx 64/32 060000h-06ffffh 030000h-037fffh sa7 000111xxx 64/32 070000h-07ffffh 038000h-03ffffh sa8 001000xxx 64/32 080000h-08ffffh 040000h-047fffh sa9 001001xxx 64/32 090000h-09ffffh 048000h-04ffffh sa10 001010xxx 64/32 0a0000h-0affffh 050000h-057fffh sa11 001011xxx 64/32 0b0000h-0bffffh 058000h-05ffffh sa12 001100xxx 64/32 0c0000h-0cffffh 060000h-067fffh sa13 001101xxx 64/32 0d0000h-0dffffh 068000h-06ffffh sa14 001110xxx 64/32 0e0000h-0effffh 070000h-077fffh sa15 001111xxx 64/32 0f0000h-0fffffh 078000h-07ffffh sa16 010000xxx 64/32 100000h-10ffffh 080000h-087fffh sa17 010001xxx 64/32 110000h-11ffffh 088000h-08ffffh sa18 010010xxx 64/32 120000h-12ffffh 090000h-097fffh sa19 010011xxx 64/32 130000h-13ffffh 098000h-09ffffh sa20 010100xxx 64/32 140000h-14ffffh 0a0000h-0a7fffh sa21 010101xxx 64/32 150000h-15ffffh 0a8000h-0affffh sa22 010110xxx 64/32 160000h-16ffffh 0b0000h-0b7fffh sa23 010111xxx 64/32 170000h-17ffffh 0b8000h-0bffffh sa24 011000xxx 64/32 180000h-18ffffh 0c0000h-0c7fffh sa25 011001xxx 64/32 190000h-19ffffh 0c8000h-0cffffh sa26 011010xxx 64/32 1a0000h-1affffh 0d0000h-0d7fffh sa27 011011xxx 64/32 1b0000h-1bffffh 0d8000h-0dffffh sa28 011100xxx 64/32 1c0000h-1cffffh 0e0000h-0e7fffh sa29 011101xxx 64/32 1d0000h-1dffffh 0e8000h-0effffh sa30 011110xxx 64/32 1e0000h-1effffh 0f0000h-0f7fffh sa31 011111xxx 64/32 1f0000h-1fffffh 0f8000h-0fffffh sa32 100000xxx 64/32 200000h-20ffffh 100000h-107fffh sa33 100001xxx 64/32 210000h-21ffffh 108000h-10ffffh sa34 100010xxx 64/32 220000h-22ffffh 110000h-117fffh sector address table (top boot block), continued
w19b320bt/b datasheet publication release date:dec.25, 2007 - 24 - revisionv a3 sector sector address a20-a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa35 100011xxx 64/32 230000h-23ffffh 118000h-11ffffh sa36 100100xxx 64/32 240000h-24ffffh 120000h-127fffh sa37 100101xxx 64/32 250000h-25ffffh 128000h-12ffffh sa38 100110xxx 64/32 260000h-26ffffh 130000h-137fffh sa39 100111xxx 64/32 270000h-27ffffh 138000h-13ffffh sa40 101000xxx 64/32 280000h-28ffffh 140000h-147fffh sa42 101010xxx 64/32 2a0000h-2affffh 150000h-157fffh sa43 101011xxx 64/32 2b0000h-2bffffh 158000h-15ffffh sa44 101100xxx 64/32 2c0000h-2cffffh 160000h-167fffh sa45 101101xxx 64/32 2d0000h-2dffffh 168000h-16ffffh sa46 101110xxx 64/32 2e0000h-2effffh 170000h-177fffh sa47 101111xxx 64/32 2f0000h-2fffffh 178000h-17ffffh sa48 110000xxx 64/32 300000h-30ffffh 180000h-187fffh sa49 110001xxx 64/32 310000h-31ffffh 188000h-18ffffh sa50 110010xxx 64/32 320000h-32ffffh 190000h-197fffh sa51 110011xxx 64/32 330000h-33ffffh 198000h-19ffffh sa52 110100xxx 64/32 340000h-34ffffh 1a0000h-1a7fffh sa53 110101xxx 64/32 350000h-35ffffh 1a8000h-1affffh sa54 110110xxx 64/32 360000h-36ffffh 1b0000h-1b7fffh sa55 110111xxx 64/32 370000h-37ffffh 1b8000h-1bffffh sa56 111000xxx 64/32 380000h-38ffffh 1c0000h-1c7fffh sa57 111001xxx 64/32 390000h-39ffffh 1c8000h-1cffffh sa58 111010xxx 64/32 3a0000h-3affffh 1d0000h-1d7fffh sa59 111011xxx 64/32 3b0000h-3bffffh 1d8000h-1dffffh sa60 111100xxx 64/32 3c0000h-3cffffh 1e0000h-1e7fffh sa61 111101xxx 64/32 3d0000h-3dffffh 1e8000h-1effffh sa62 111110xxx 64/32 3e0000h-3effffh 1f0000h-1f7fffh sa63 111111000 8/4 3f0000h-3f1fffh 1f8000h-1f8fffh sa64 111111001 8/4 3f2000h-3f3fffh 1f9000h-1f9fffh sa65 111111010 8/4 3f4000h-3f5fffh 1fa000h-1fafffh sa66 111111011 8/4 3f6000h-3f7fffh 1fb000h-1fbfffh sa67 111111100 8/4 3f8000h-3f9fffh 1fc000h-1fcfffh sa68 111111101 8/4 3fa000h-3fbfffh 1fd000h-1fdfffh sa69 111111110 8/4 3fc000h-3fdfffh 1fe000h-1fefffh sa70 111111111 8/4 3fe000h-3fffffh 1ff000h-1fffffh note : the address range is [a20: a-1] in byte mode (#byte =v il ) or [a20:a0] in word mode (#byte = v ih ).
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 25 - revisionv a3 security sector addresses for top boot devices device sector address a20-a12 sector size (bytes/words) (x 8) address range (x 16) address range w19b320bt/b 111111xxx 256/128 3fe000h-3fe0ffh 1ff000h-1ff07fh 7.4 sector address table (bottom boot block) sector sector address a20-a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 000000000 8/4 000000h-001fffh 000000h-000fffh sa1 000000001 8/4 002000h-003fffh 001000h-001fffh sa2 000000010 8/4 004000h-005fffh 002000h-002fffh sa3 000000011 8/4 006000h-007fffh 003000h-003fffh sa4 000000100 8/4 008000h-009fffh 004000h-004fffh sa5 000000101 8/4 00a000h-00bfffh 005000h-005fffh sa6 000000110 8/4 00c000h-00dfffh 006000h-006fffh sa7 000000111 8/4 00e000h- 00ffffh 007000h-007fffh sa8 000001xxx 64/32 010000h- 01ffffh 008000h-00ffffh sa9 000010xxx 64/32 020000h- 02ffffh 010000h-017fffh sa10 000011xxx 64/32 030000h- 03ffffh 018000h-01ffffh sa11 000100xxx 64/32 040000h- 04ffffh 020000h-027fffh sa12 000101xxx 64/32 050000h- 05ffffh 028000h-02ffffh sa13 000110xxx 64/32 060000h- 06ffffh 030000h-037fffh sa14 000111xxx 64/32 070000h- 07ffffh 038000h-03ffffh sa15 001000xxx 64/32 080000h- 08ffffh 040000h-047fffh sa16 001001xxx 64/32 090000h- 09ffffh 048000h-04ffffh sa17 001010xxx 64/32 0a0000h- 0affffh 050000h-057fffh sa18 001011xxx 64/32 0b0000h- 0bffffh 058000h-05ffffh sa19 001100xxx 64/32 0c 0000h-0cffffh 060000h-067fffh sa20 001101xxx 64/32 0d 0000h-0dffffh 068000h-06ffffh sa21 001110xxx 64/32 0e0000h- 0effffh 070000h-077fffh sa22 001111xxx 64/32 0f0000h- 0fffffh 078000h-07ffffh sa23 010000xxx 64/32 100000h- 10ffffh 080000h-087fffh sa24 010001xxx 64/32 110000h- 11ffffh 088000h-08ffffh sa25 010010xxx 64/32 120000h- 12ffffh 090000h-097fffh sa26 010011xxx 64/32 130000h- 13ffffh 098000h-09ffffh sa27 010100xxx 64/32 140000h-14 ffffh 0a0000h-0a7fffh sa28 010101xxx 64/32 150000h-15 ffffh 0a8000h-0affffh sa29 010110xxx 64/32 160000h-16 ffffh 0b0000h-0b7fffh sa30 010111xxx 64/32 170000h-17 ffffh 0b8000h-0bffffh sa31 011000xxx 64/32 180000h-18 ffffh 0c0000h-0c7fffh
w19b320bt/b datasheet publication release date:dec.25, 2007 - 26 - revisionv a3 sector address table (bottom boot block), continued sector sector address a20-a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa32 011001xxx 64/32 190000h-19 ffffh 0c8000h-0cffffh sa33 011010xxx 64/32 1a0000h-1a ffffh 0d0000h-0d7fffh sa34 011011xxx 64/32 1b0000h- 1bffffh 0d8000h-0dffffh sa35 011100xxx 64/32 1c0000h- 1cffffh 0e0000h-0e7fffh sa36 011101xxx 64/32 1d0000h- 1dffffh 0e8000h-0effffh sa37 011110xxx 64/32 1e0000h-1e ffffh 0f0000h-0f7fffh sa38 011111xxx 64/32 1f0000h- 1fffffh 0f8000h-0fffffh sa39 100000xxx 64/32 200000h- 20ffffh 100000h-107fffh sa40 100001xxx 64/32 210000h- 21ffffh 108000h-10ffffh sa41 100010xxx 64/32 220000h- 22ffffh 110000h-117fffh sa42 100011xxx 64/32 230000h- 23ffffh 118000h-11ffffh sa43 100100xxx 64/32 240000h- 24ffffh 120000h-127fffh sa44 100101xxx 64/32 250000h- 25ffffh 128000h-12ffffh sa45 100110xxx 64/32 260000h- 26ffffh 130000h-137fffh sa46 100111xxx 64/32 270000h- 27ffffh 138000h-13ffffh sa47 101000xxx 64/32 280000h- 28ffffh 140000h-147fffh sa48 101001xxx 64/32 290000h- 29ffffh 148000h-14ffffh sa49 101010xxx 64/32 2a0000h- 2affffh 150000h-157fffh sa50 101011xxx 64/32 2b0000h- 2bffffh 158000h-15ffffh sa51 101100xxx 64/32 2c 0000h-2cffffh 160000h-167fffh sa52 101101xxx 64/32 2d 0000h-2dffffh 168000h-16ffffh sa53 101110xxx 64/32 2e0000h- 2effffh 170000h-177fffh sa54 101111xxx 64/32 2f0000h- 2fffffh 178000h-17ffffh sa55 111000xxx 64/32 300000h- 30ffffh 180000h-187fffh sa56 110001xxx 64/32 310000h- 31ffffh 188000h-18ffffh sa57 110010xxx 64/32 320000h- 32ffffh 190000h-197fffh sa58 110011xxx 64/32 330000h- 33ffffh 198000h-19ffffh sa59 110100xxx 64/32 340000h-34 ffffh 1a0000h-1a7fffh sa60 110101xxx 64/32 350000h-35 ffffh 1a8000h-1affffh sa61 110110xxx 64/32 360000h-36 ffffh 1b0000h-1b7fffh sa62 110111xxx 64/32 370000h-37 ffffh 1b8000h-1bffffh sa63 111000xxx 64/32 380000h-38 ffffh 1c0000h-1c7fffh sa64 111001xxx 64/32 390000h-39 ffffh 1c8000h-1cffffh sa65 111010xxx 64/32 3a0000h-3a ffffh 1d0000h-1d7fffh sa65 111011xxx 64/32 3b0000h- 3bffffh 1d8000h-1dffffh sa67 111100xxx 64/32 3c0000h- 3cffffh 1e0000h-1e7fffh sa68 111101xxx 64/32 3d0000h- 3dffffh 1e8000h-1effffh sa69 111110xxx 64/32 3e0000h-3e ffffh 1f0000h-1f7fffh sa70 111111xxx 64/32 3f0000h- 3fffffh 1f8000h-1fffffh note: the address range is [a20: a-1] in byte mode (#byte =v il ) or [a20:a0] in word mode (#byte =v ih ).
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 27 - revisionv a3 security sector addresses for bottom boot devices device sector address a20-a12 sector size (bytes/words) (x8) address range (x16) address range w19b320bt/b 000000xxx 256/128 000000h-0000ffh 000000h-00007fh 7.5 top boot sector/sector block address for protection/unprotection) sector a20-a12 sector/sector block size sa0-sa3 000000xxx 000001xxx 000010xxx 000011xxx 256(4x64) k bytes sa4-sa7 0001xxxxx 256(4x64) k bytes sa8-sa11 0010xxxxx 256(4x64) k bytes sa12-sa15 0011xxxxx 256(4x64) k bytes sa16-sa19 0100xxxxx 256(4x64) k bytes sa20-sa23 0101xxxxx 256(4x64) k bytes sa24-sa27 0110xxxxx 256(4x64) k bytes sa28-sa31 0111xxxxx 256(4x64) k bytes sa32-sa35 1000xxxxx 256(4x64) k bytes sa36-sa39 1001xxxxx 256(4x64) k bytes sa40-sa43 1010xxxxx 256(4x64) k bytes sa44-sa47 1011xxxxx 256(4x64) k bytes sa48-sa51 1100xxxxx 256(4x64) k bytes sa52-sa55 1101xxxxx 256(4x64) k bytes sa56-sa59 1110xxxxx 256(4x64) k bytes sa60-sa62 111100xxx 111101xxx 111110xxx 192(3x64) k bytes sa63 111111000 8 k bytes sa64 111111001 8 k bytes sa65 111111010 8 k bytes sa66 111111011 8 k bytes sa67 111111100 8 k bytes sa68 111111101 8 k bytes sa69 111111110 8 k bytes sa70 111111111 8 k bytes
w19b320bt/b datasheet publication release date:dec.25, 2007 - 28 - revisionv a3 bottom boot sector/sector block a ddress for protection/unprotection) sector a20-a12 sector/sector block size sa70-sa67 111111xxx 111110xxx 111101xxx 111100xxx 256(4x64) k bytes sa66-sa63 1110xxxxx 256(4x64) k bytes sa62-sa59 1101xxxxx 256(4x64) k bytes sa58-sa55 1100xxxxx 256(4x64) k bytes sa54-sa51 1011xxxxx 256(4x64) k bytes sa50-sa47 1010xxxxx 256(4x64) k bytes sa46-sa43 1001xxxxx 256(4x64) k bytes sa42-sa39 1000xxxxx 256(4x64) k bytes sa38-sa35 0111xxxxx 256(4x64) k bytes sa34-sa31 0110xxxxx 256(4x64) k bytes sa30-sa27 0101xxxxx 256(4x64) k bytes sa26-sa23 0100xxxxx 256(4x64) k bytes sa22-sa19 0011xxxxx 256(4x64) k bytes sa18-sa15 0010xxxxx 256(4x64) k bytes sa14-sa11 0001xxxxx 256(4x64) k bytes sa10-sa8 000011xxx 000010xxx 000001xxx 192(3x64) k bytes sa7 000000111 8 k bytes sa6 000000110 8 k bytes sa5 000000101 8 k bytes sa4 000000100 8 k bytes sa3 000000011 8 k bytes sa2 000000010 8 k bytes sa1 000000001 8 k bytes sa0 000000000 8 k bytes
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 29 - revisionv a3 7.6 cfi query identification string description address (word mode) data address (byte mode) query-unique ascii string "qry" 10h 11h 12h 0051h 0052h 0059h 20h 22h 24h primary oem command set 13h 14h 0002h 0000h 26h 28h address for primary extended table 15h 16h 0040h 0000h 2ah 2ch alternate oem command set (00h = none exists) 17h 18h 0000h 0000h 2eh 30h address for alternative oem extended table (00h = none exists) 19h 1ah 0000h 0000h 32h 34h 7.6.1 system interface string description address (word mode) data address (byte mode) v dd min. (write/erase) d7-d4: volt , d3-d0: 100 mv 1bh 0027h 36h v dd max. (write/erase) d7-d4: volt , d3-d0: 100 mv 1ch 0036h 38h v pp min. voltage (00h=no v pp pin present) 1dh 0000h 3ah v pp max. voltage (00h=no v pp pin present) 1eh 0000h 3ch typical timeout per single byte/word write 2 n s 1fh 0004h 3eh typical timeout for min. size buffer write 2 n s (00h=not supported) 20h 0000h 40h typical timeout per individual block erase 2 n ms 21h 000ah 42h typical timeout for full chip erase 2 n ms (00h=not supported) 22h 0000h 44h max. timeout for byte/word write 2 n times typical 23h 0005h 46h max. timeout for buffer write 2 n times typical 24h 0000h 48h max. timeout per individual block erase 2 n times typical 25h 0004h 4ah max. timeout for full chip erase 2 n times typical ( 00h = not supported) 26h 0000h 4ch
w19b320bt/b datasheet publication release date:dec.25, 2007 - 30 - revisionv a3 7.6.2 device geometry definition description address (word mode) data address (byte mode) device size =2 n bytes 27h 0016h 4eh flash device interface description (refer to cfi publication 100) 28h 29h 0002h 0000h 50h 52h max. number of bytes in multi-byte write=2 n (00h=not supported) 2ah 2bh 0000h 0000h 54h 56h number of erase block regions within devices 2ch 0002h 58h erase block region 1 information (refer to the cfi specification or cfi publication 100 ) 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h 5ah 5ch 5eh 60h erase block region 2 information 31h 32h 33h 34h 003eh 0000h 0000h 0001h 62h 64h 66h 68h erase block region 3 information 35h 36h 37h 38h 0000h 0000h 0000h 0000h 6ah 6ch 6eh 70h erase block region 4 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h 72h 74h 76h 78h
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 31 - revisionv a3 7.6.3 primary vendor-specific extended query description address (word mode) data address ( byte mode) query-unique ascii string "pri" 40h 41h 42h 0050h 0052h 0049h 80h 82h 84h major version number, ascii 43h 0031h 86h minor version number, ascii 44h 0033h 88h silicon revision number 01h = 0.13 m 45h 0001h 8ah erase suspend 0 = not supported, 1= to read only; 2 = to read & write 46h 0002h 8ch sector protect 00 = not supported, 01=supported 47h 0001h 8eh sector temporary unprotect 00 = not supported, 01=supported 48h 0001h 90h sector protect/unpr otect scheme 49h 0004h 92h simultaneous operation number of sectors (except for bank 1) 4ah 0038h 94h burst mode type 00 = not supported, 01=supported 4bh 0000h 96h page mode type 00 = not supported, 01=4 word page, 02=8 word page 4ch 0000h 98h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4dh 0085h 9ah acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 0095h 9ch top/bottom boot sector flag 02h=bottom boot device, 03h=top boot device 4fh 000xh 9eh
w19b320bt/b datasheet publication release date:dec.25, 2007 - 32 - revisionv a3 7.6.4 command definitions bus cycles (note 2-5) first second third fourth fifth sixth command sequence (note 1 ) cycle addr data addr data addr data addr data addr data a dd r data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 word 555 2aa 555 normal program byte 4 aaa aa 555 55 aaa a0 pa pd word 555 2aa 555 unlock bypass byte 3 aaa aa 555 55 aaa 20 unlock bypass program (note 11) 2 xxx a0 pa pd unlock bypass reset (note12) 2 xxx 90 xxx 00 word 555 2aa 555 555 2aa 555 chip erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 word 555 2aa 555 555 2aa sector erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 erase suspend (note 13) 1 xxx b0 erase resume (note 14) 1 xxx 30 word 555 2aa 555 manufacturer code byte 4 aaa aa 555 55 aaa 90 x00 da word 555 2aa 55 x01 device code byte 4 aaa aa 555 55 aaa 90 x02 (note 16) word 555 2aa 555 x03 security sector factory protect (note 9) byte 4 aaa aa 555 55 aaa 90 x06 82/02 word 555 2aa 555 x02 autoselect(note8) sector/sector block protect verify (note 10) byte 4 aaa aa 555 55 aaa 90 x04 00/01 word 555 2aa 555 enter security sector region byte 3 aaa aa 555 55 aaa 88 word 555 2aa 555 exit security sector region byte 4 aaa aa 555 55 aaa 90 xxx 00 word 55 common flash interface (cfi) query (note 15) byte 1 aa 98 legend: x = don?t care ra = address of the memory location to be read. pa = address of the memory location to be programmed. a ddresses latch on the falling edge of the #we or #ce pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of #we or #c e pulse, whichever happens first. rd = data read from location ra during read operation. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a20-a12 uniquely select any sector.
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 33 - revisionv a3 notes: 1. see bus operations table for details. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15-dq8 are don?t care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a20-a11 are ?don?t care?. 6. no unlock or command cycles requi red when bank is reading array data. 7. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when the device is in the autoselect mode, or if dq5 goes high (while the dev ice is providing status information). 8. the fourth cycle of the autoselect command sequence is a read cycle. data bits dq15-dq8 are don?t care. see the autoselect command sequence section for more information. 9. the data is 82h for factory locked and 02h for not factory locked. 10. the data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 11. the unlock bypass command is required pr ior to the unlock bypass program command. 12. the unlock bypass reset command is required to return to the read mode when the bank is in the unlock bypass mode. 13. the system may read and program in non-erasing sector s, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is va lid only during a sector erase operation. 14. the erase resume command is valid only during the erase suspend mode. 15. command is valid when device is ready to read array data or when device is in autoselect mode. 16. see autoselect codes table for device id information 7.6.5 write operation status status dq7 (note 2) dq6 dq5 (note1) dq3 dq2 (note 2) ry/#by embedded program algorithm #dq7 toggle 0 n/a no toggle 0 standard mode embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspended sector 1 no toggle 0 n/a toggle 1 erase- suspend read non-erase suspended sector data data data data data 1 erase suspend mode erase-suspend-program #dq7 toggle 0 n/a n/a 0 notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has ex ceeded the maximum timing limits. refer to dq5 description section for more information. 2. dq7 and dq2 require a valid address when reading status info rmation. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs a rray data if the system addresses a non-busy bank. 7.7 temporary sector unprotect algorithm
w19b320bt/b datasheet publication release date:dec.25, 2007 - 34 - revisionv a3 start #reset = v id (note 1) perform erase or program operations #reset = v ih temporary sector unprotect completed (note 2) notes: 1. all protected sectors unprotected (if #wp/acc = vi l, outermost boot sectors will remain protected). 2. all previously protected se ctors are protected once again.
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 35 - revisionv a3 7.8 in-system sector protect/unprotect algorithms start plscnt=1 #reset=v id wait 1 s first write cycle=60h? wait 150 s verity sector protect:write 40h to sector address with a6=0, a1=1,a0=0 set up sector address yes sector protect: write 60h to sector address with a6=0,a1=1,a0=0 read from sector address with a6=0, a1=1,a0=0 remove v from #reset id write reset command sector protect complete protect another sector? data=01h? temporary sector unprotect mode increment plscnt plscnt =25? no no device failed yes yes no reset plscnt=1 start plscnt=1 #reset=v id wait 1 s first write cycle=60h? yes all sectors protected ? yes wait 15 ms verity sector unprotect:write 40h to sector address with a6=1, a1=1,a0=0 sector unprotect: write 60h to any address with a6=1,a1=1,a0=0 read from sector address with a6=1, a1=1,a0=0 remove v from #reset id write reset command last sector verified data=00h? no yes no set up first sector address protect all sectors the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address temporary sector unprotect mode no no increment plscnt plscnt =1000? device failed yes sector unprotect complete set up next sector address yes sector protect algorithm sector unprotect algorithm no yes no
w19b320bt/b datasheet publication release date:dec.25, 2007 - 36 - revisionv a3 7.9 security sector protect verify start write 60h to any address write 40h to security sector address with a6 = 0 a1 = 1, a0 = 0 read from security sector address with a6 = 0 a1 = 1, a0 = 0 if data = 00h, security sector is unprotected. if data = 01h, security sector is producted. remove v ih or v id from #reset write reset command security sector protect verify complete #reset = v ih v id or wait 1 s enter security sector exit security sector 7.10 program algorithm start write program command sequence data poll from system verify data? increment address yes last address? yes programming completed embedded program algorithm in progress no no
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 37 - revisionv a3 7.11 erase algorithm start write program command sequence data poll to erasing bank from system data=ffh? erase completed (note1,2) no yes embedded erase algorithm in progress notes: 1. see command definitions table for erase command sequence details. 2. see dq3 section for the sector erase timer details. 7.12 data polling algorithm start read dq7-dq0 addr=va dq7=data? no dq5=1? yes no dq7=data? read dq7-dq0 addr=va fail pass yes yes no notes: 1. va = valid address for programming. during a sector erase operation; a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
w19b320bt/b datasheet publication release date:dec.25, 2007 - 38 - revisionv a3 7.13 toggle bit algorithm start read dq7-dq0 toggle bit no dq5=1? yes no toggle bit read dq7-dq0 twice yes yes no read dq7-dq0 =toggle? =toggle? program/erase operation not complete,write reset command program/erase complete note: the system should recheck the toggle bit even if dq5 =?1? because the toggle bit may st op toggling as dq5 changes to ?1?. see dq6 and dq2 section for more information
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 39 - revisionv a3 8. electrical characteristics 8.1 absolute maximum ratings parameter rating unit storage temperature plastic packages -65 to +150 c ambient temperature with power applied -65 to +125 c v dd (note 1) -0.5 to +4.0 v a9, #oe, and #reset (note 2) -0.5 to +11.5 v #wp/acc -0.5 to +10.5 v voltage with respect to ground all other pins (note 1) -0.5 to v dd +0.5 v output short circuit current (note 3) 200 ma notes: 1. minimum dc voltage on input or i/o pins is -0.5 v. du ring voltage transitions, input or i/o pins may overshoot v ss to - 2.0 v for periods of up to 20 ns. maximu m dc voltage on input or i/o pins is v dd +0.5 v. during voltage transitions, input or i/o pins may overshoot to v dd +2.0 v for periods up to 20 ns. 2. minimum dc input voltage on pins a9, #oe, #reset, and #w p/acc is -0.5 v. during voltage transitions, a9, #oe, #wp/acc, and #reset may overshoot v ss to -2.0 v for periods of up to 20 ns . maximum dc input voltage on pin a9 is +11.5 v which may overshoot to +14.0 v for periods up to 20 ns. maximum dc input voltage on #wp/acc is +9.5 v which may overshoot to +12.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time . duration of the short circ uit should not be greater than one second. stresses above those listed under ?abs olute maximum ratings? may caus e permanent damage to the device. this is a stress rating only; functi onal operation of the devic e at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 8.2 operating ranges parameter rating unit industrial grade -40 to +85 ambient temperature (ta ) extended grade -20 to +85 c v dd supply voltages v dd for standard voltage range 2.7 to 3.6 v operating ranges define t hose limits between which the functionality of t he device is guaranteed.
w19b320bt/b datasheet publication release date:dec.25, 2007 - 40 - revisionv a3 8.3 dc characteristics 8.4 cmos compatible limits parameter sym. test conditions min. typ. max. unit input load current i li v in =v ss to v dd , v dd = v dd (max.) - - 1.0 a a9 input load current i lit v dd = v dd (max.), a9 = v id (max.) - - 35 a output leakage current i lo v out =v ss to v dd , v dd =v dd (max.) - - 1.0 a 5 mhz - 10 16 ma #ce = v il, #oe = v ih byte mode 1 mhz 2 4 ma 5 mhz 10 16 ma v dd active read current (note 1, 2) i cc1 #ce = v il , #oe = v ih word mode 1 mhz 2 4 ma v dd active write current (note 2, 3) i cc2 #ce = v il, #oe = v ih, #we = v il - 15 30 ma v dd standby current (note2,5) i cc3 #ce = v dd 0.3v, #reset = v dd 0.3v - 0.2 5 a v dd reset current (note2) i cc4 #reset = v ss 0.3v - 0.2 5 a automatic sleep mode current (note 2, 4,5) i cc5 v ih = v dd 0.3v, v il = v ss 0.3v - 0.2 5 a v dd active program-while- erase-suspended current (note 2, 6) i cc6 #ce = v il, #oe = v ih - 17 35 ma acc pin 5 10 ma acc accelerated program current, word or byte i acc #ce = v il, #oe = v ih v dd pin 15 30 ma input low voltage v il - -0.5 - 0.8 v input high voltage v ih - 0.7x v dd - v dd +0.3 v voltage for #wp/acc sector protect/ unprotect and program acceleration v hh v dd =3.0v 10% 8.5 - 9.5 v voltage for autoselect and temporary sector unprotected v id v dd =3.0v 10% 8.5 - 11.5 v output low voltage v ol i ol = 4.0 ma, v dd = v dd (min.) - - 0.45 v v oh1 i oh = -2.0 ma, v dd = v dd (min.) 0.85 v dd - - v output high voltage v oh2 i oh = -100 a, v dd = v dd (min.) v dd - 0.4 - - notes: 1. the i cc current listed is typically less than 2 ma/ mhz, with #oe at v ih . 2. maximum i cc specifications are tested with v dd = v dd max. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is200 na. 5. for temperature >70 degree c, vih( max.)=vdd+0.1v and vil(min)=vss-0.1v. 6. not 100% tested
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 41 - revisionv a3 8.5 ac characteristics 8.6 test condition test condition 70ns unit output load 1 ttl gate output load capacitance, cl (inc luding jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0-3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v 8.6.1 ac test load and waveforms +3.3v 2.7k 6.2k d out 30 pf (including jig and scope) input 3v 0v test point test point 1.5v 1.5v output
w19b320bt/b datasheet publication release date:dec.25, 2007 - 42 - revisionv a3 8.7 read-only operations 70ns parameter sym. test setup min. max. unit read cycle time t rc 70 - ns address to output delay t acc #oe, #ce =v il - 70 ns chip enable to output delay t ce #oe, = v il - 70 ns output enable to output delay t oe - 30 ns chip enable to output high z t df - 16 ns output enable to output high z t df - 16 ns output hold time from address, #oe or #ce , whichever occurs first t oh 0 - ns read 0 - ns output enable hold time toggle and #data polling t oeh 10 - ns note: not 100 % tested 8.8 hardware reset (#reset) parameter sym. min. max. unit #reset pin low (during embedded algorithms) to read mode t ready - 20 s #reset pin low (not during embedded algorithms) to read mode t ready - 500 ns #reset pulse width t rp 500 - ns reset high time before read t rh 50 - ns #reset low to standby mode t rpd 20 - s ry/#by recovery time t rb 0 - ns note: not 100 % tested 8.9 word/byte configuration (#byte) 70ns parameter sym. min. max. unit #ce to #byte switching low or high t elfl /t elfh - 5 ns #byte switching low to output high z t flqz - 16 ns #byte switching high to output active t fhqv 70 - ns
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 43 - revisionv a3 8.10 erase and program operation 70ns parameter sym. min. typ. max. unit write cycle timing (note 1) t wc 70 - - ns address setup time t as 0 - - ns address setup timing to #oe low during toggle bit polling t aso 15 - - ns address hold time t ah 45 - - ns address hold time from #ce or #oe high during toggle bit polling t aht 0 - - ns data setup time t ds 35 - - ns data hold time t dh 0 - - ns output enable high during toggle bit polling t oeph 20 - - ns read recovery time before write ( #oe high to #we low) t ghwl 0 - - ns #ce setup time t cs 0 - - ns #ce hold time t ch 0 - - ns write pulse width t wp 30 - - ns write pulse width high t wph 30 - - ns latency between read and write operation t sr/w 0 - - ns byte t pb - 7 150 s programming time (note 2) word t pw - 9 210 s byte accelerated programming time (noe2) word t accp 4 - s sector erase time (note 2) t se - 0.4 - sec v dd setup time (note 1) t vcs 50 - - s write recovery time from ry/#by t rb 0 - - ns program/erase valid to ry/#by delay t busy 90 - - ns notes: 1. not 100 % tested 2. see the ?alternate #ce controlled erase and progr am operations? section for more information 8.11 temporary sector unprotect parameter sym. min. max. unit vid rise and fall time t vidr 500 - ns vhh rise and fall time t vhh 250 - ns #reset setup time for temporary sector unprotect t rsp 4 - s #reset hold time from ry/#by high for temporary sector unprotect t rrb 4 - s note: not 100 % tested
w19b320bt/b datasheet publication release date:dec.25, 2007 - 44 - revisionv a3 8.12 alternate #ce controlled erase and program operations 70 ns parameter sym. min. typical (note3) max. (note4) unit write cycle time (note 1) t wc 70 - - ns address setup time t as 0 - - ns address hold time t ah 45 - - ns data setup time t ds 35 - - ns data hold time t dh 0 - - ns read recover time before write (#oe high to #we low) t ghel 0 - - ns #we setup time t ws 0 - - ns #we hold time t wh 0 - - ns #ce pulse width t cp 30 - - ns #ce pulse width high t cph 30 - - ns byte t pb - 7 150 programming time (note 6) word t pw - 9 210 s byte accelerated programming time (note 6) word t accp - 4 120 s sector erase time (note 2) t se - 0.4 15 sec chip erase time (note 2) t ce - 30 - sec byte t cpb - 21 63 chip program time (note 5) word t cpw - 14 42 sec notes: 1. not 100 % tested. 2. in the pre-programming step of the embedded erase algor ithm, all bytes are programmed to 00h before erasure. 3. typical program and erase time assume the following conditions :25 ,3.0 v v dd , 100,000 cycles .additionally, programming typicals assume checkerboard pattern. 4. under worst case conditions of 90 , v dd =2.7v, 100,000 cycles. 5. the typical chip programming time is considerably less than the maximun chip programming time listed,since most bytes program faster than maximun program times listed. 6. system-level overhead is the time r equired to execute the two- or four-bus -cycle sequence for the program command. 7. the device has a minimum erase and program cycle endurance of 100,000 cycles.
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 45 - revisionv a3 9. timing waveforms 9.1 ac read waveform address outputs high-z #ce #oe #we t rc t oe t acc t oh t df high-z addresses stable t rh t rh t oeh t ce 0v #reset ry/#by output valid 9.2 reset waveform rp t t rh t ready reset timing not during embedded algorithms #reset ry/#by #oe,#ce t ready t rp t rb reset timings during embedded algorithms #reset ry/#by #oe,#ce
w19b320bt/b datasheet publication release date:dec.25, 2007 - 46 - revisionv a3 9.3 #byte waveform for read operation dq0-dq14 dq15/a-1 data output (dq0-dq14) dq15 output (dq0-dq7) data output address input dq0-dq14 dq15 output address input dq15/a-1 data output (dq0-dq14) (dq0-dq7) data output t elfl t flqz t elfh t fhqv #oe #ce #byte #byte switching from word to byte mode #byte switching from byte to word mode #byte 9.4 #byte waveform for write operation t set t hold as (t ) (t ah ) note: refer to the erase /program operations table for tas and tah specifications. #ce #byte #we the falling edge of the last #we signal
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 47 - revisionv a3 9.5 programming waveform 555h pa pa pa a ddress t wc t as t ch t ah t wp program command sequence (last two cycles) read status data (last two cycles) status d out pd a0h t cs t dh t wph t busy t rb t vcs data vdd ry/#by #we #oe #ce ds t t pw notes: 1. pa = program address, pd = program data,d out is the true data at the program address 2. illustration shows device in word mode 9.6 accelerated programming waveform v hh v il v ih or t vhh t vhh v il v ih or #wp/acc
w19b320bt/b datasheet publication release date:dec.25, 2007 - 48 - revisionv a3 9.7 chip/sector erase waveform 2aah sa va va t wc t as t ch t ah t wp t cs t ds t dh t wph t se erase command sequence (last two cycles) read status data 30h 55h t busy t rb t vcs progress in complete 10 for chip erase 555h for chip erase address data vdd ry/#by #we #oe #ce notes : 1. sa = sector address (for sector er ase), va = valid address for reading stat us data (see ?write operation status?). 2. these waveforms are for the word mode 9.8 back-to back read/write cycle waveform t wc t rc t wc t wc t cp t cph t ce t acc t oe t oeh t wp t wph t ds t dh t sr/w t oh t df valid in out valid valid pa valid ra valid pa valid pa t ah valid in valid in t ghwl #we controlled write cycle read cycle #ce controlled write cycle addresses data #we #oe #ce
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 49 - revisionv a3 9.9 #data polling waveform (during embedded algorithms) t rc valid data va t ce t acc t oe t oeh t busy t oh t ch t df addresses dq0-dq6 va va valid data high z high z dq7 status data complement true status data complement true ry/#by #we #oe #ce note: va= valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. 9.10 toggle bit waveform (during embedded algorithms) addresses dq6/dq2 valid data valid data valid status valid status valid status (stop toggling) t oe t oeh t ceph t oeph t dh t aso t aht t as t aht ry/#by #we #oe #ce (first read) (second read) note: va= valid address;not requires for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
w19b320bt/b datasheet publication release date:dec.25, 2007 - 50 - revisionv a3 9.11 dq 2 vs. dq6 waveform #we erase suspend dq2 dq6 enter embedded erasing read erase suspend erase enter erase suspend program erase suspend program erase suspend read erase erase erase resume complete note: dq2 toggles only when read at an address within an erase- suspended sector. the sysytem may use #oe or #ce to toggle dq2 and dq6. 9.12 temporary sector unprotect timing diagram t rsp t vidr v il v ss ih v or , , t rrb t vidr v il v ss ih v or , , v id v id program or erase command sequence #reset #ce #we ry/#by 9.13 sector/sector block protect and unprotect timing diagram data valid* a1,a0 sa,a6, #reset *for sector protect,a6=0,a1=1,a0=0.for sector unprotect ,a6=1,a1=1,a0=0 sector/sector block protect:150 s, sector/sector block unprotect:15ms 1 s sector/sector block protect or unprotect v id v ih 60h 60h valid* valid* 40h verify status #ce #we #oe
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 51 - revisionv a3 9.14 alternate #ce controlled write (erase/program) operation timing . . d out #dq7 #reset data address 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase #data polling pa t wc t as t ah t wh t ghel t cp t ws t ds t dh a0 for program 55 for erase pd for program 30 for sector erase 10 for chip erase t busy t rh #we #oe #ce ry/#by t cph t pw, t accp, or t se notes: 1. firgure indicates last two bus cycl es of a program or erase operation. 2. pa= program address, sa= sect or address, pd= program data. 3. #dq7 is the complement of the data written to the device. dout is the data written to the device. 4. waveforms are for the word mode.
w19b320bt/b datasheet publication release date:dec.25, 2007 - 52 - revisionv a3 10. latchup characteristics parameter min. max. input voltage with respect to v ss on all pins except i/o pins (including a9, #oe, and #reset) -1.0v 11.5 v input voltage with respect to v ss on all i/o pins -1.0v v dd +1.0v v dd current -100ma +100ma note : includes all pins except v dd . test conditions: v dd = 3.0 v, one pin at a time. 11. capacitance tsop tfbga parameter sym. test setup typical max. typical max. unit input capacitance cin vin = 0 6 7.5 4.2 5.0 pf output capacitance cout vout = 0 8.5 12 5.4 6.5 pf control pin capacitance cin2 vin = 0 7.5 9 3.9 4.7 pf notes: 1. sampled, not 100 % tested. 2. test condition ta = 25 c, f = 1.0 mhz.
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 53 - revisionv a3 12. ordering information notes: 1. winbond reserves the right to make c hanges to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
w19b320bt/b datasheet publication release date:dec.25, 2007 - 54 - revisionv a3 13. package dimensions 13.1 tfbga48ball (6x8 mm^2, ?=0.40mm)
w19b320bt/b datasheet publication release date:dec. 25, 2007 - 55 - revisionv a3 13.2 48-pin standard thin small outline package 0.020 0.004 0.007 0.037 0.002 min. 0.60 y l l1 c 0.50 0.10 0.70 0.21 millimeter a a2 b a1 0.95 0.17 0.05 sym. min. 1.20 0.27 1.05 1.00 0.22 max. nom. 0.028 0.008 0.024 0.011 0.041 0.047 0.009 0.039 nom. inch max. e h d 0 5 0 5 e d 18.3 18.4 18.5 19.8 20.0 20.2 11.9 12.0 12.1 0.720 0.724 0.728 0.780 0.787 0.795 0.468 0.472 0.476 0.10 0.80 0.031 0.004 0.020 0.50 e 1 48 b e d y a1 a a2 l1 l c h d
w19b320bt/b datasheet publication release date:dec.25, 2007 - 56 - revisionv a3 14. version history version date page description a0 dec,31, 2006 all initial issued ,note p21 a1 june,15,2007 all 1. vid was changed from 12.5 to 11.5 2. erase time was changed form 49 sec to 30sec 3. re-typesetting a2 oct,17,2007 46 update package material as green a3 dec.25,2007 41,44,45 1. add note 5 and 6 2. add max of tpb and tpw 3. modify format and setting important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.

▲Up To Search▲

Price & Availability of W19B320BB

	To Download W19B320BB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .